<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#content { width: 100%; margin: }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label {  min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="content">
<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Gowin Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\Cortex-M3-DualCam\impl\gwsynthesis\gowin_empu_m3.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\Cortex-M3-DualCam\src\dual_5640.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">GOWIN version</td>
<td>V1.9.8</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Nov 29 13:28:02 2021
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>53563</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>30442</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>80</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>227</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>92</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>sys_clk_ibuf/I </td>
</tr>
<tr>
<td>SWCLK</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I </td>
</tr>
<tr>
<td>cam0_pclk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>cam0_pclk_ibuf/I </td>
</tr>
<tr>
<td>cam1_pclk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>cam1_pclk_ibuf/I </td>
</tr>
<tr>
<td>cam0_vsync</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>cam0_vsync_ibuf/I </td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/n344_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/n344_s2/F </td>
</tr>
<tr>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1/Q </td>
</tr>
<tr>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1/Q </td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q </td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>300.000</td>
<td>3.333
<td>0.000</td>
<td>150.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>150.000</td>
<td>6.667
<td>0.000</td>
<td>75.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>30.000</td>
<td>33.333
<td>0.000</td>
<td>15.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>5.000</td>
<td>200.000
<td>0.000</td>
<td>2.500</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>5.000</td>
<td>200.000
<td>0.000</td>
<td>2.500</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>15.000</td>
<td>66.667
<td>0.000</td>
<td>7.500</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>2.692</td>
<td>371.429
<td>0.000</td>
<td>1.346</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>2.692</td>
<td>371.429
<td>0.000</td>
<td>1.346</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>5.385</td>
<td>185.714
<td>0.000</td>
<td>2.692</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>8.077</td>
<td>123.810
<td>0.000</td>
<td>4.038</td>
<td>sys_clk_ibuf/I</td>
<td>sys_clk</td>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>13.462</td>
<td>74.286
<td>0.000</td>
<td>6.731</td>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT</td>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT </td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>50.000(MHz)</td>
<td>188.230(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>SWCLK</td>
<td>100.000(MHz)</td>
<td style="color: #FF0000;">78.721(MHz)</td>
<td>13</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>cam0_pclk</td>
<td>100.000(MHz)</td>
<td style="color: #FF0000;">84.372(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>cam1_pclk</td>
<td>100.000(MHz)</td>
<td style="color: #FF0000;">92.250(MHz)</td>
<td>13</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>cam0_vsync</td>
<td>100.000(MHz)</td>
<td>539.554(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2</td>
<td>100.000(MHz)</td>
<td>157.163(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2</td>
<td>100.000(MHz)</td>
<td>177.066(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>8</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
<td>100.000(MHz)</td>
<td>410.455(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>9</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
<td>20.000(MHz)</td>
<td>24.216(MHz)</td>
<td>30</td>
<td>TOP</td>
</tr>
<tr>
<td>10</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>100.000(MHz)</td>
<td>319.577(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>11</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
<td>200.000(MHz)</td>
<td>2016.130(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>12</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>74.286(MHz)</td>
<td>115.128(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>13</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>50.000(MHz)</td>
<td>95.853(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/n344_6!</h4>
<h4>No timing paths to get frequency of Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sys_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SWCLK</td>
<td>Setup</td>
<td>-65.662</td>
<td>40</td>
</tr>
<tr>
<td>SWCLK</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cam0_pclk</td>
<td>Setup</td>
<td>-11.434</td>
<td>16</td>
</tr>
<tr>
<td>cam0_pclk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cam1_pclk</td>
<td>Setup</td>
<td>-0.840</td>
<td>1</td>
</tr>
<tr>
<td>cam1_pclk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cam0_vsync</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>cam0_vsync</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/n344_6</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/n344_6</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-8.287</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_1_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>17.088</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-7.951</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.752</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-7.904</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.705</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-7.802</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.603</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-7.767</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.568</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-7.767</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.568</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-7.767</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.568</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-7.767</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.568</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-7.762</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.562</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-7.616</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.417</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-7.596</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.397</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-7.596</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.397</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-7.596</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.397</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-7.590</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.391</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-7.590</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.391</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-7.590</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CE</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.391</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-7.582</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.383</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-7.552</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.353</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-7.552</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.353</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-7.470</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.270</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-7.415</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.216</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-7.415</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.216</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-7.289</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.089</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-7.206</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>16.006</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-7.046</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0/D</td>
<td>SWCLK:[R]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>10.000</td>
<td>1.129</td>
<td>15.846</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-1.442</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/n63_s2/I</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1/D</td>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2:[R]</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.631</td>
<td>0.234</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-1.442</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/n63_s2/I</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1/D</td>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2:[R]</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.631</td>
<td>0.234</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-1.350</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0/D</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0/D</td>
<td>cam0_vsync:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.304</td>
<td>0.000</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-1.039</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_5_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_5_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.462</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-1.039</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_8_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_8_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.462</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-0.804</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.697</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-0.804</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_1_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_1_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.697</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-0.804</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_6_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_6_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.697</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-0.697</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_7_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_7_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.804</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-0.684</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_2_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.818</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-0.682</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_3_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.819</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-0.652</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_9_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_9_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.849</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-0.437</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>0.770</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-0.426</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>0.781</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-0.407</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_4_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_4_s0/D</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>1.095</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-0.304</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>0.904</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-0.286</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>0.921</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-0.280</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>0.927</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-0.209</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_0_s0/CE</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>-0.626</td>
<td>0.464</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-0.209</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_1_s0/CE</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>-0.626</td>
<td>0.464</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-0.143</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>1.064</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-0.142</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>1.065</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-0.134</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>1.073</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-0.124</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>1.083</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-0.121</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/CALIB</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.172</td>
<td>1.086</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-2.829</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_22_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.134</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-2.829</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.134</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-2.829</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_26_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.134</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-2.829</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_28_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.134</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-2.829</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_30_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.134</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-2.824</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.128</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-2.824</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.128</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-2.824</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.128</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-2.824</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.128</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-2.824</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_23_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.128</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-2.824</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_24_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>3.128</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-2.151</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.456</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-2.151</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.456</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-2.151</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.456</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-2.151</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.456</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-2.120</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.425</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-2.081</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.386</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-1.903</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.207</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-1.903</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.207</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-1.903</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.207</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-1.903</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.207</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-1.838</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.143</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-1.838</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>2.143</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-1.596</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d2_0_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>1.900</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-1.596</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d1_0_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.385</td>
<td>0.010</td>
<td>1.900</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-0.878</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_32b_5_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.623</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-0.878</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_16b_d1_5_s0/CLEAR</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>cam0_pclk:[R]</td>
<td>0.000</td>
<td>-1.455</td>
<td>0.623</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-0.778</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-2.064</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-0.778</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-2.064</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-0.778</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-2.064</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-0.778</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-2.064</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-0.778</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-2.064</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-0.778</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-2.064</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-0.410</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.696</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-0.410</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.696</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-0.410</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.696</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-0.410</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.696</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-0.410</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.696</td>
<td>1.474</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-0.410</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-1.696</td>
<td>1.474</td>
</tr>
<tr>
<td>15</td>
<td>0.762</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.524</td>
<td>1.474</td>
</tr>
<tr>
<td>16</td>
<td>0.762</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.524</td>
<td>1.474</td>
</tr>
<tr>
<td>17</td>
<td>0.762</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.524</td>
<td>1.474</td>
</tr>
<tr>
<td>18</td>
<td>0.762</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.524</td>
<td>1.474</td>
</tr>
<tr>
<td>19</td>
<td>0.762</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.524</td>
<td>1.474</td>
</tr>
<tr>
<td>20</td>
<td>0.762</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>-0.524</td>
<td>1.474</td>
</tr>
<tr>
<td>21</td>
<td>1.692</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-2.500</td>
<td>-2.096</td>
<td>1.474</td>
</tr>
<tr>
<td>22</td>
<td>1.692</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-2.500</td>
<td>-2.096</td>
<td>1.474</td>
</tr>
<tr>
<td>23</td>
<td>1.692</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-2.500</td>
<td>-2.096</td>
<td>1.474</td>
</tr>
<tr>
<td>24</td>
<td>1.692</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-2.500</td>
<td>-2.096</td>
<td>1.474</td>
</tr>
<tr>
<td>25</td>
<td>1.692</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
<td>-2.500</td>
<td>-2.096</td>
<td>1.474</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/ShiftReg_12_s0</td>
</tr>
<tr>
<td>2</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_6_s0</td>
</tr>
<tr>
<td>3</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_5_s0</td>
</tr>
<tr>
<td>4</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_1_s0</td>
</tr>
<tr>
<td>5</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Trnmode_cdc_check_0_s0</td>
</tr>
<tr>
<td>6</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_31_s0</td>
</tr>
<tr>
<td>7</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/DPaddr_1_s0</td>
</tr>
<tr>
<td>8</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_22_s0</td>
</tr>
<tr>
<td>9</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_17_s0</td>
</tr>
<tr>
<td>10</td>
<td>2.786</td>
<td>3.786</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>SWCLK</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_14_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-8.287</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.907</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s4/I1</td>
</tr>
<tr>
<td>58.215</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R73C65[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s4/F</td>
</tr>
<tr>
<td>58.385</td>
<td>0.170</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C64[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBnext_1_s6/I1</td>
</tr>
<tr>
<td>58.940</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R73C64[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBnext_1_s6/F</td>
</tr>
<tr>
<td>59.337</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C66[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBnext_1_s5/I1</td>
</tr>
<tr>
<td>59.907</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C66[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBnext_1_s5/F</td>
</tr>
<tr>
<td>59.907</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C66[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C66[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_1_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_1_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R73C66[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.966, 40.763%; route: 9.890, 57.879%; tC2Q: 0.232, 1.358%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.951</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.571</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.537</td>
<td>0.466</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C64[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_2_s1/I3</td>
</tr>
<tr>
<td>58.999</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C64[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_2_s1/F</td>
</tr>
<tr>
<td>59.001</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_2_s0/I0</td>
</tr>
<tr>
<td>59.571</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_2_s0/F</td>
</tr>
<tr>
<td>59.571</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R73C64[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.987, 41.707%; route: 9.533, 56.908%; tC2Q: 0.232, 1.385%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.904</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.524</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.988</td>
<td>0.406</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C63[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s3/I2</td>
</tr>
<tr>
<td>58.505</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C63[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s3/F</td>
</tr>
<tr>
<td>58.918</td>
<td>0.413</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s4/I0</td>
</tr>
<tr>
<td>59.380</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s4/F</td>
</tr>
<tr>
<td>59.524</td>
<td>0.144</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C66[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C66[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C66[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/APBcurr_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.449, 38.603%; route: 10.024, 60.008%; tC2Q: 0.232, 1.389%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.802</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.422</td>
<td>0.545</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C64[0][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C64[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R76C64[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.159%; route: 9.869, 59.443%; tC2Q: 0.232, 1.397%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.767</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.387</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.387</td>
<td>0.510</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R76C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.242%; route: 9.834, 59.358%; tC2Q: 0.232, 1.400%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.767</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.387</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.387</td>
<td>0.510</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C64[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.242%; route: 9.834, 59.358%; tC2Q: 0.232, 1.400%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.767</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.387</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.387</td>
<td>0.510</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[2][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.242%; route: 9.834, 59.358%; tC2Q: 0.232, 1.400%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.767</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.387</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.387</td>
<td>0.510</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R76C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.242%; route: 9.834, 59.358%; tC2Q: 0.232, 1.400%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.381</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.381</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C64[2][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R71C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.256%; route: 9.829, 59.344%; tC2Q: 0.232, 1.401%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.616</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.236</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.774</td>
<td>0.703</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R76C64[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_4_s0/I1</td>
</tr>
<tr>
<td>59.236</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R76C64[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_4_s0/F</td>
</tr>
<tr>
<td>59.236</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C64[0][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C64[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R76C64[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.417, 39.086%; route: 9.768, 59.501%; tC2Q: 0.232, 1.413%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.596</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.216</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.216</td>
<td>0.339</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[1][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_7_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C65[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.651%; route: 9.663, 58.934%; tC2Q: 0.232, 1.415%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.596</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.216</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.216</td>
<td>0.339</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[2][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C65[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.651%; route: 9.663, 58.934%; tC2Q: 0.232, 1.415%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.596</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.216</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.216</td>
<td>0.339</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.651%; route: 9.663, 58.934%; tC2Q: 0.232, 1.415%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.590</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.210</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.210</td>
<td>0.333</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C65[0][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R71C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.666%; route: 9.657, 58.919%; tC2Q: 0.232, 1.415%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.590</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.210</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.210</td>
<td>0.333</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R73C64[1][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.666%; route: 9.657, 58.919%; tC2Q: 0.232, 1.415%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.590</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.210</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.582</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.844</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/I1</td>
</tr>
<tr>
<td>58.306</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s3/F</td>
</tr>
<tr>
<td>58.307</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/I0</td>
</tr>
<tr>
<td>58.877</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R73C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s2/F</td>
</tr>
<tr>
<td>59.210</td>
<td>0.333</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R73C64[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.502, 39.666%; route: 9.657, 58.919%; tC2Q: 0.232, 1.415%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.582</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.202</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.277</td>
<td>0.206</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C64[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_5_s1/I3</td>
</tr>
<tr>
<td>58.739</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C64[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_5_s1/F</td>
</tr>
<tr>
<td>58.740</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_5_s0/I0</td>
</tr>
<tr>
<td>59.202</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R72C64[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_5_s0/F</td>
</tr>
<tr>
<td>59.202</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C64[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.879, 41.987%; route: 9.272, 56.597%; tC2Q: 0.232, 1.416%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.552</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.172</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.602</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R76C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_0_s0/I1</td>
</tr>
<tr>
<td>59.172</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R76C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_0_s0/F</td>
</tr>
<tr>
<td>59.172</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R76C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.525, 39.900%; route: 9.596, 58.682%; tC2Q: 0.232, 1.419%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.552</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.172</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.602</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R76C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s0/I0</td>
</tr>
<tr>
<td>59.172</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R76C65[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s0/F</td>
</tr>
<tr>
<td>59.172</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R76C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R76C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.525, 39.900%; route: 9.596, 58.682%; tC2Q: 0.232, 1.419%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.470</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.089</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.519</td>
<td>0.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R73C64[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_3_s0/I0</td>
</tr>
<tr>
<td>59.089</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R73C64[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_3_s0/F</td>
</tr>
<tr>
<td>59.089</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R73C64[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R73C64[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.525, 40.102%; route: 9.514, 58.472%; tC2Q: 0.232, 1.426%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.415</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.035</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.110</td>
<td>0.039</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C65[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_8_s1/I3</td>
</tr>
<tr>
<td>58.481</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C65[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_8_s1/F</td>
</tr>
<tr>
<td>58.486</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C65[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_8_s0/I0</td>
</tr>
<tr>
<td>59.035</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C65[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_8_s0/F</td>
</tr>
<tr>
<td>59.035</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[2][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C65[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.875, 42.395%; route: 9.109, 56.175%; tC2Q: 0.232, 1.431%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.415</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>59.035</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.110</td>
<td>0.039</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C65[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_11_s1/I3</td>
</tr>
<tr>
<td>58.481</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C65[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_11_s1/F</td>
</tr>
<tr>
<td>58.486</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_11_s0/I0</td>
</tr>
<tr>
<td>59.035</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C65[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_11_s0/F</td>
</tr>
<tr>
<td>59.035</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[1][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C65[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>16</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.875, 42.395%; route: 9.109, 56.175%; tC2Q: 0.232, 1.431%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.289</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>58.908</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.537</td>
<td>0.466</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_6_s0/I0</td>
</tr>
<tr>
<td>58.908</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R71C64[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_6_s0/F</td>
</tr>
<tr>
<td>58.908</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C64[2][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R71C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.326, 39.316%; route: 9.532, 59.242%; tC2Q: 0.232, 1.442%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.206</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>58.826</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.277</td>
<td>0.206</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_1_s0/I1</td>
</tr>
<tr>
<td>58.826</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R71C65[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_1_s0/F</td>
</tr>
<tr>
<td>58.826</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C65[0][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R71C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R71C65[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.504, 40.631%; route: 9.271, 57.919%; tC2Q: 0.232, 1.449%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.046</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>58.666</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.620</td>
</tr>
<tr>
<td class="label">From</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>SWCLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>40.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>325</td>
<td>IOB17[B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>42.819</td>
<td>2.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C48[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/CLK</td>
</tr>
<tr>
<td>43.051</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>19</td>
<td>R72C48[0][A]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/State_cdc_check_2_s0/Q</td>
</tr>
<tr>
<td>43.486</td>
<td>0.435</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C50[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/I2</td>
</tr>
<tr>
<td>43.939</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R72C50[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s2/F</td>
</tr>
<tr>
<td>44.879</td>
<td>0.940</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C44[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/I1</td>
</tr>
<tr>
<td>45.434</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>R72C44[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwjWatcher/DBGDI_s1/F</td>
</tr>
<tr>
<td>46.839</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C57[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/I3</td>
</tr>
<tr>
<td>47.394</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R72C57[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s2/F</td>
</tr>
<tr>
<td>47.926</td>
<td>0.531</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C51[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/I0</td>
</tr>
<tr>
<td>48.297</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>30</td>
<td>R72C51[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dap_ahb_ap/u_cm3_dap_ahb_ap_slv/dap_trans_valid_s1/F</td>
</tr>
<tr>
<td>50.544</td>
<td>2.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R71C71[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/I3</td>
</tr>
<tr>
<td>50.997</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R71C71[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/dap_rdata_28_s1/F</td>
</tr>
<tr>
<td>51.807</td>
<td>0.810</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C72[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/I1</td>
</tr>
<tr>
<td>52.377</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R74C72[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n263_s0/COUT</td>
</tr>
<tr>
<td>52.377</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R74C73[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/CIN</td>
</tr>
<tr>
<td>52.412</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R74C73[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n264_s0/COUT</td>
</tr>
<tr>
<td>52.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[0][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/CIN</td>
</tr>
<tr>
<td>52.448</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[0][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n265_s0/COUT</td>
</tr>
<tr>
<td>52.448</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C73[1][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/CIN</td>
</tr>
<tr>
<td>52.483</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C73[1][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n266_s0/COUT</td>
</tr>
<tr>
<td>53.637</td>
<td>1.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/I0</td>
</tr>
<tr>
<td>54.090</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R74C62[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Cmplane_3_s2/F</td>
</tr>
<tr>
<td>54.580</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R74C66[2][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/I0</td>
</tr>
<tr>
<td>55.097</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R74C66[2][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/n272_s0/COUT</td>
</tr>
<tr>
<td>55.968</td>
<td>0.871</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/I3</td>
</tr>
<tr>
<td>56.339</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C66[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s6/F</td>
</tr>
<tr>
<td>56.343</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/I1</td>
</tr>
<tr>
<td>56.892</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R72C66[3][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s5/F</td>
</tr>
<tr>
<td>57.065</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[3][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/I3</td>
</tr>
<tr>
<td>57.614</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R72C65[3][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntEn_s4/F</td>
</tr>
<tr>
<td>57.618</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C65[0][A]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/I2</td>
</tr>
<tr>
<td>58.071</td>
<td>0.453</td>
<td>tINS</td>
<td>RF</td>
<td>12</td>
<td>R72C65[0][A]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_10_s5/F</td>
</tr>
<tr>
<td>58.295</td>
<td>0.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_9_s0/I0</td>
</tr>
<tr>
<td>58.666</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R72C64[2][B]</td>
<td style=" background: #97FFFF;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/BuscntD_9_s0/F</td>
</tr>
<tr>
<td>58.666</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R72C64[2][B]</td>
<td style=" font-weight:bold;">Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>51.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>5240</td>
<td>PLL_R[1]</td>
<td>Cortex_M3/u_Gowin_rPLL/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>51.690</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R72C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CLK</td>
</tr>
<tr>
<td>51.655</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0</td>
</tr>
<tr>
<td>51.620</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R72C64[2][B]</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPDpApbIf/Buscnt_cdc_check_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.129</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 24.210%; route: 2.137, 75.790%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.326, 39.918%; route: 9.289, 58.618%; tC2Q: 0.232, 1.464%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.442</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.234</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.677</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/n63_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u1_ov5640_dri/dri_clk_2</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>46</td>
<td>R44C24[0][A]</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1/Q</td>
</tr>
<tr>
<td>0.002</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C24[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/n63_s2/I</td>
</tr>
<tr>
<td>0.234</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R44C24[0][A]</td>
<td style=" background: #97FFFF;">graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/n63_s2/O</td>
</tr>
<tr>
<td>0.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C24[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>PLL_R[2]</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.631</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C24[0][A]</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1/CLK</td>
</tr>
<tr>
<td>1.666</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1</td>
</tr>
<tr>
<td>1.677</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R44C24[0][A]</td>
<td>graphics_processing_unit/u1_ov5640_dri/u_i2c_dr/dri_clk_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.631</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 98.957%; route: 0.000, 0.000%; tC2Q: 0.002, 1.043%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.442</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.234</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.677</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/n63_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u0_ov5640_dri/dri_clk_2</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>46</td>
<td>R57C23[0][A]</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1/Q</td>
</tr>
<tr>
<td>0.002</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R57C23[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/n63_s2/I</td>
</tr>
<tr>
<td>0.234</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R57C23[0][A]</td>
<td style=" background: #97FFFF;">graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/n63_s2/O</td>
</tr>
<tr>
<td>0.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R57C23[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>PLL_R[2]</td>
<td>graphics_processing_unit/u_cmos_rpll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.631</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R57C23[0][A]</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1/CLK</td>
</tr>
<tr>
<td>1.666</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1</td>
</tr>
<tr>
<td>1.677</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R57C23[0][A]</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_i2c_dr/dri_clk_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.631</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 98.957%; route: 0.000, 0.000%; tC2Q: 0.002, 1.043%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.350</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.675</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>cam0_vsync:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_vsync</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB52[A]</td>
<td>cam0_vsync_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>IOB52[A]</td>
<td>cam0_vsync_ibuf/O</td>
</tr>
<tr>
<td>0.675</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB52[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB52[A]</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOB52[A]</td>
<td>graphics_processing_unit/u0_ov5640_dri/u_cmos_capture_data/cam_vsync_d0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.304</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 100.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.039</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.986</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C22[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_5_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R34C22[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_5_s0/Q</td>
</tr>
<tr>
<td>0.986</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C21[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C21[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_5_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_5_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C21[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.039</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.986</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C17[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_8_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R34C17[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_8_s0/Q</td>
</tr>
<tr>
<td>0.986</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C15[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C15[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_8_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_8_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C15[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.804</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C24[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R32C24[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s0/Q</td>
</tr>
<tr>
<td>1.221</td>
<td>0.495</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C25[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C25[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C25[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.495, 71.035%; tC2Q: 0.202, 28.965%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.804</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C24[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R32C24[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_1_s0/Q</td>
</tr>
<tr>
<td>1.221</td>
<td>0.495</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C25[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C25[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_1_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_1_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C25[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.495, 71.035%; tC2Q: 0.202, 28.965%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.804</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C18[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_6_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R35C18[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_6_s0/Q</td>
</tr>
<tr>
<td>1.221</td>
<td>0.495</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C17[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C17[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_6_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_6_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C17[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.495, 71.035%; tC2Q: 0.202, 28.965%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.697</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.328</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C21[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_7_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R34C21[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_7_s0/Q</td>
</tr>
<tr>
<td>1.328</td>
<td>0.602</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C24[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C24[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_7_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_7_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C24[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.602, 74.883%; tC2Q: 0.202, 25.117%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.684</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.341</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C21[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s0/CLK</td>
</tr>
<tr>
<td>0.725</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R34C21[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s0/Q</td>
</tr>
<tr>
<td>1.341</td>
<td>0.617</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R33C22[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C22[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_2_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_2_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C22[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.617, 75.414%; tC2Q: 0.201, 24.586%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.682</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.343</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C22[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_3_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R34C22[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_3_s0/Q</td>
</tr>
<tr>
<td>1.343</td>
<td>0.617</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C24[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C24[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_3_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_3_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C24[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.617, 75.347%; tC2Q: 0.202, 24.653%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.652</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.373</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C24[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_9_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R34C24[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_9_s0/Q</td>
</tr>
<tr>
<td>1.373</td>
<td>0.647</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C16[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C16[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_9_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_9_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C16[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.647, 76.210%; tC2Q: 0.202, 23.790%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.437</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.293</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.293</td>
<td>0.568</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL28[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.568, 73.758%; tC2Q: 0.202, 26.242%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.426</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.304</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.304</td>
<td>0.579</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL29[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[7].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.579, 74.130%; tC2Q: 0.202, 25.870%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.407</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.618</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C20[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_4_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R34C20[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_4_s0/Q</td>
</tr>
<tr>
<td>1.618</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C23[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C23[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_4_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_4_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C23[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.893, 81.546%; tC2Q: 0.202, 18.454%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.304</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.427</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.427</td>
<td>0.702</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL32[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[3].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.702, 77.643%; tC2Q: 0.202, 22.357%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.286</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.445</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.445</td>
<td>0.719</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL33[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[4].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.719, 78.074%; tC2Q: 0.202, 21.926%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.280</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.451</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.451</td>
<td>0.725</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL35[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL35[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL35[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[1].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.725, 78.216%; tC2Q: 0.202, 21.784%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.209</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.987</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.196</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[2][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R7C11[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0/Q</td>
</tr>
<tr>
<td>0.987</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C10[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR44[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>47</td>
<td>IOR44[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>1.150</td>
<td>0.475</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C10[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_0_s0/CLK</td>
</tr>
<tr>
<td>1.185</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_0_s0</td>
</tr>
<tr>
<td>1.196</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C10[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.626</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 58.734%; route: 0.475, 41.266%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.209</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.987</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.196</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[2][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R7C11[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_init_complete_d_1_s0/Q</td>
</tr>
<tr>
<td>0.987</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C10[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR44[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>47</td>
<td>IOR44[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>1.150</td>
<td>0.475</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C10[0][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_1_s0/CLK</td>
</tr>
<tr>
<td>1.185</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_1_s0</td>
</tr>
<tr>
<td>1.196</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C10[0][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/uddcntln_d_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.626</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 58.734%; route: 0.475, 41.266%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.143</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.587</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[2][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0/Q</td>
</tr>
<tr>
<td>1.587</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL47[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL47[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL47[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[5].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.862, 81.008%; tC2Q: 0.202, 18.992%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.142</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.588</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.588</td>
<td>0.863</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL44[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL44[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL44[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[0].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.863, 81.030%; tC2Q: 0.202, 18.970%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.134</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.596</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.596</td>
<td>0.871</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL43[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL43[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL43[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.871, 81.170%; tC2Q: 0.202, 18.830%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.124</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.606</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[2][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_0_s0/Q</td>
</tr>
<tr>
<td>1.606</td>
<td>0.881</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL46[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL46[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL46[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[2].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.881, 81.342%; tC2Q: 0.202, 18.658%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.121</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.610</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.731</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C10[1][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R21C10[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ides_calib_reg_1_s0/Q</td>
</tr>
<tr>
<td>1.610</td>
<td>0.884</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL42[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem</td>
</tr>
<tr>
<td>1.731</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/iserdes_gen[6].u_ides8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.172</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.884, 81.402%; tC2Q: 0.202, 18.598%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.829</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.717</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.717</td>
<td>2.902</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C14[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_22_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C14[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_22_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_22_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C14[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.902, 92.597%; tC2Q: 0.232, 7.403%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.829</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.717</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.717</td>
<td>2.902</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C14[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C14[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C14[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.902, 92.597%; tC2Q: 0.232, 7.403%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.829</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.717</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_26_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.717</td>
<td>2.902</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C14[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_26_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C14[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_26_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_26_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C14[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_26_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.902, 92.597%; tC2Q: 0.232, 7.403%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.829</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.717</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_28_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.717</td>
<td>2.902</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C14[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_28_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C14[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_28_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_28_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C14[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_28_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.902, 92.597%; tC2Q: 0.232, 7.403%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.829</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.717</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_30_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.717</td>
<td>2.902</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C14[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_30_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C14[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_30_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_30_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C14[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_30_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.902, 92.597%; tC2Q: 0.232, 7.403%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.711</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.711</td>
<td>2.896</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C15[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C15[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C15[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.896, 92.583%; tC2Q: 0.232, 7.417%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.711</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.711</td>
<td>2.896</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C14[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C14[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C14[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.896, 92.583%; tC2Q: 0.232, 7.417%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.711</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.711</td>
<td>2.896</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C14[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C14[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C14[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.896, 92.583%; tC2Q: 0.232, 7.417%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.711</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.711</td>
<td>2.896</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C15[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C15[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C15[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.896, 92.583%; tC2Q: 0.232, 7.417%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.711</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.711</td>
<td>2.896</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C15[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_23_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C15[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_23_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_23_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C15[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.896, 92.583%; tC2Q: 0.232, 7.417%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.711</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.711</td>
<td>2.896</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C15[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_24_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C15[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_24_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_24_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C15[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.896, 92.583%; tC2Q: 0.232, 7.417%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.151</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.038</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.038</td>
<td>2.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C13[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C13[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C13[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.224, 90.552%; tC2Q: 0.232, 9.448%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.151</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.038</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.038</td>
<td>2.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C13[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C13[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C13[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.224, 90.552%; tC2Q: 0.232, 9.448%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.151</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.038</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.038</td>
<td>2.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C13[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C13[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C13[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.224, 90.552%; tC2Q: 0.232, 9.448%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.151</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.038</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.038</td>
<td>2.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C13[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C13[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C13[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.224, 90.552%; tC2Q: 0.232, 9.448%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.120</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.007</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>43.007</td>
<td>2.193</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C5[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C5[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C5[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.193, 90.431%; tC2Q: 0.232, 9.569%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.081</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.969</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.969</td>
<td>2.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C12[1][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C12[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C12[1][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.154, 90.276%; tC2Q: 0.232, 9.724%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.903</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.790</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.790</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C13[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C13[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C13[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.975, 89.489%; tC2Q: 0.232, 10.511%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.903</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.790</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.790</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C12[1][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C12[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C12[1][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.975, 89.489%; tC2Q: 0.232, 10.511%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.903</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.790</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.790</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C12[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C12[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C12[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.975, 89.489%; tC2Q: 0.232, 10.511%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.903</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.790</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.790</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C12[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C12[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C12[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.975, 89.489%; tC2Q: 0.232, 10.511%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.726</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.726</td>
<td>1.911</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C11[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C11[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C11[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.911, 89.174%; tC2Q: 0.232, 10.826%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.838</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.726</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.726</td>
<td>1.911</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C11[2][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C11[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C11[2][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.911, 89.174%; tC2Q: 0.232, 10.826%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.596</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.483</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d2_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.483</td>
<td>1.668</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C9[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d2_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C9[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d2_0_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d2_0_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C9[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d2_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.668, 87.792%; tC2Q: 0.232, 12.208%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.596</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.483</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d1_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>40.583</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>40.815</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>42.483</td>
<td>1.668</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C9[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d1_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.385</td>
<td>40.385</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.385</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.714</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>196</td>
<td>TOPSIDE[0]</td>
<td>graphics_processing_unit/u_Gowin_CLKDIV/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.957</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C9[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d1_0_s0/CLK</td>
</tr>
<tr>
<td>40.922</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d1_0_s0</td>
</tr>
<tr>
<td>40.887</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C9[2][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_d1_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.010</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.385</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.668, 87.792%; tC2Q: 0.232, 12.208%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.243, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.878</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.147</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_32b_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>1.147</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C11[0][B]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_32b_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C11[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_32b_5_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_32b_5_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R37C11[0][B]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_32b_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.421, 67.577%; tC2Q: 0.202, 32.423%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.878</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.147</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.025</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_16b_d1_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>cam0_pclk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C10[2][A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK</td>
</tr>
<tr>
<td>0.726</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>583</td>
<td>R27C10[2][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q</td>
</tr>
<tr>
<td>1.147</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C11[0][A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_16b_d1_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>cam0_pclk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>804</td>
<td>IOB73[A]</td>
<td>cam0_pclk_ibuf/O</td>
</tr>
<tr>
<td>1.979</td>
<td>1.304</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C11[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_16b_d1_5_s0/CLK</td>
</tr>
<tr>
<td>2.014</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_16b_d1_5_s0</td>
</tr>
<tr>
<td>2.025</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R37C11[0][A]</td>
<td>graphics_processing_unit/Video_Frame_Buffer/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_d_16b_d1_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.455</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.421, 67.577%; tC2Q: 0.202, 32.423%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 34.133%; route: 1.304, 65.867%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.252</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL37[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>2.064</td>
<td>0.368</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>2.064</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>2.099</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td>2.252</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.064</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.524, 84.890%; route: 0.093, 15.110%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.252</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL29[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>2.064</td>
<td>0.368</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>2.064</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>2.099</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td>2.252</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.064</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.524, 84.890%; route: 0.093, 15.110%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.252</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL42[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>2.064</td>
<td>0.368</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>2.064</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>2.099</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td>2.252</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.064</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.524, 84.890%; route: 0.093, 15.110%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.252</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL28[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>2.064</td>
<td>0.368</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>2.064</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>2.099</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td>2.252</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.064</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.524, 84.890%; route: 0.093, 15.110%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.252</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL33[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>2.064</td>
<td>0.368</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>2.064</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>2.099</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td>2.252</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.064</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.524, 84.890%; route: 0.093, 15.110%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.778</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.252</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL32[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>2.064</td>
<td>0.368</td>
<td>tINS</td>
<td>RR</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>2.064</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>2.099</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td>2.252</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.064</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.524, 84.890%; route: 0.093, 15.110%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL37[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td>1.884</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL29[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td>1.884</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL42[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td>1.884</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL28[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td>1.884</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL33[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td>1.884</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL32[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>1.446</td>
<td>1.446</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.446</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>1.602</td>
<td>0.156</td>
<td>tINS</td>
<td>RR</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>1.696</td>
<td>0.093</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/FCLK</td>
</tr>
<tr>
<td>1.731</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td>1.884</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.696</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.156, 62.583%; route: 0.093, 37.417%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>21.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL37[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>20.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>20.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK</td>
</tr>
<tr>
<td>20.559</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td>20.712</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>21.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL29[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>20.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>20.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK</td>
</tr>
<tr>
<td>20.559</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td>20.712</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>21.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL42[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>20.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>20.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK</td>
</tr>
<tr>
<td>20.559</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td>20.712</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>21.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL28[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>20.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>20.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/PCLK</td>
</tr>
<tr>
<td>20.559</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td>20.712</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>21.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL33[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>20.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>20.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/PCLK</td>
</tr>
<tr>
<td>20.559</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td>20.712</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.762</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>21.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL32[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>20.339</td>
<td>0.339</td>
<td>tCL</td>
<td>RR</td>
<td>1652</td>
<td>LEFTSIDE[0]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>20.524</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem/PCLK</td>
</tr>
<tr>
<td>20.559</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
<tr>
<td>20.712</td>
<td>0.153</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL32[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[3].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.692</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-0.218</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL37[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-2.500</td>
<td>-2.500</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-2.500</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-1.054</td>
<td>1.446</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-1.054</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>-0.892</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>-0.793</td>
<td>0.099</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.389</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>-0.369</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
<tr>
<td>-0.218</td>
<td>0.151</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL37[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[8].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.096</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-2.500</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.551, 84.834%; route: 0.099, 15.166%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.692</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-0.218</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL29[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-2.500</td>
<td>-2.500</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-2.500</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-1.054</td>
<td>1.446</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-1.054</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>-0.892</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>-0.793</td>
<td>0.099</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.389</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>-0.369</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
<tr>
<td>-0.218</td>
<td>0.151</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL29[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[7].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.096</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-2.500</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.551, 84.834%; route: 0.099, 15.166%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.692</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-0.218</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL42[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-2.500</td>
<td>-2.500</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-2.500</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-1.054</td>
<td>1.446</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-1.054</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>-0.892</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>-0.793</td>
<td>0.099</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.389</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>-0.369</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
<tr>
<td>-0.218</td>
<td>0.151</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL42[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[6].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.096</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-2.500</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.551, 84.834%; route: 0.099, 15.166%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.692</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-0.218</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL28[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-2.500</td>
<td>-2.500</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-2.500</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-1.054</td>
<td>1.446</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-1.054</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>-0.892</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>-0.793</td>
<td>0.099</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.389</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>-0.369</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
<tr>
<td>-0.218</td>
<td>0.151</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL28[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[5].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.096</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-2.500</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.551, 84.834%; route: 0.099, 15.166%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.692</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>-0.218</td>
</tr>
<tr>
<td class="label">From</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">To</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/ddr_rst</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1171</td>
<td>R9C12[0][B]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/ddr_rsti_reg_2_s0/Q</td>
</tr>
<tr>
<td>1.474</td>
<td>1.474</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>IOL33[A]</td>
<td style=" font-weight:bold;">graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>-2.500</td>
<td>-2.500</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>-2.500</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>-1.054</td>
<td>1.446</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>PLL_R[0]</td>
<td>graphics_processing_unit/pll_ddr3/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>-1.054</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>3</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKIN</td>
</tr>
<tr>
<td>-0.892</td>
<td>0.162</td>
<td>tINS</td>
<td>FF</td>
<td>64</td>
<td>-</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/fclk_dhcen/CLKOUT</td>
</tr>
<tr>
<td>-0.793</td>
<td>0.099</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.389</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R35C0</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/DQSW270</td>
</tr>
<tr>
<td>-0.404</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem/TCLK</td>
</tr>
<tr>
<td>-0.369</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
<tr>
<td>-0.218</td>
<td>0.151</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOL33[A]</td>
<td>graphics_processing_unit/DDR3_MIG/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/oserdes_gen[4].u_oser8_mem</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.096</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-2.500</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 1.474, 100.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.551, 84.834%; route: 0.099, 15.166%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/ShiftReg_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/ShiftReg_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/ShiftReg_12_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_6_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_5_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_5_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_5_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPSwDpProtocol/TrnferCnt_cdc_check_1_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Trnmode_cdc_check_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Trnmode_cdc_check_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Trnmode_cdc_check_0_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_31_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_31_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_31_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/DPaddr_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/DPaddr_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/DPaddr_1_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_22_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_22_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_22_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_17_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_17_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_17_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.786</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.786</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>SWCLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_14_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>8.640</td>
<td>2.952</td>
<td>tNET</td>
<td>FF</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_14_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>SWCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/JTAG_9_ibuf/O</td>
</tr>
<tr>
<td>12.425</td>
<td>1.750</td>
<td>tNET</td>
<td>RR</td>
<td>Cortex_M3/u_Gowin_EMPU_M3_Top/u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/Buswdatai_cdc_check_14_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>5240</td>
<td>MCU_SYS_CLK</td>
<td>1.393</td>
<td>0.261</td>
</tr>
<tr>
<td>2551</td>
<td>n88_5</td>
<td>38.080</td>
<td>8.244</td>
</tr>
<tr>
<td>1652</td>
<td>dma_clk</td>
<td>-2.829</td>
<td>0.261</td>
</tr>
<tr>
<td>1490</td>
<td>poreset_n_qq</td>
<td>38.707</td>
<td>2.782</td>
</tr>
<tr>
<td>1171</td>
<td>ddr_rst</td>
<td>-0.238</td>
<td>2.681</td>
</tr>
<tr>
<td>804</td>
<td>cam0_pclk_d</td>
<td>-1.852</td>
<td>2.534</td>
</tr>
<tr>
<td>645</td>
<td>lsu_state_ex[2]</td>
<td>14.191</td>
<td>4.459</td>
</tr>
<tr>
<td>595</td>
<td>lsu_state_ex[1]</td>
<td>13.490</td>
<td>4.030</td>
</tr>
<tr>
<td>583</td>
<td>init_calib_complete</td>
<td>1.226</td>
<td>3.439</td>
</tr>
<tr>
<td>578</td>
<td>lsu_state_ex[0]</td>
<td>13.505</td>
<td>5.584</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R53C65</td>
<td>93.06%</td>
</tr>
<tr>
<td>R46C44</td>
<td>91.67%</td>
</tr>
<tr>
<td>R50C44</td>
<td>91.67%</td>
</tr>
<tr>
<td>R62C36</td>
<td>90.28%</td>
</tr>
<tr>
<td>R64C33</td>
<td>90.28%</td>
</tr>
<tr>
<td>R64C34</td>
<td>90.28%</td>
</tr>
<tr>
<td>R43C44</td>
<td>90.28%</td>
</tr>
<tr>
<td>R56C26</td>
<td>90.28%</td>
</tr>
<tr>
<td>R52C35</td>
<td>90.28%</td>
</tr>
<tr>
<td>R48C47</td>
<td>90.28%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
</div><!-- content -->
</body>
</html>
